PCB board anti-ESD design

Anti-ESD design method of PCB board in electronic equipment

In the design process of electronic products, designers usually start to consider the problem of anti-static discharge (ESD) when the product enters the production process. In order to make electronic equipment pass the anti-static discharge test without destroying the original design, the final solution usually uses expensive components, manual assembly during the manufacturing process, and even a redesign of the PCB board. progress is bound to be affected. Therefore, in the process of designing the PCB board of electronic products, it is necessary to consider the problem of optimizing ESD protection.

1. The impact of ESD on electronic equipment

Anti-electrostatic discharge (ESD) design rules must be followed in the design of electronic products, because most electronic devices are in an environment full of ESD for 99% of their lifespan, especially in the current portable products. Low-power logic chips, most of them are designed and manufactured based on CMOS technology, due to the metal oxide semiconductor (MOS) dielectric breakdown and bipolar reverse junction current limitation, these IC chips are very sensitive to ESD. Additionally, most I/O ports (especially USB ports) are hot-swappable systems that are highly susceptible to ESD from the user or from air discharge. ESD can come from the human body, furniture, or even inside the device itself. Although it is rare for electronic equipment to be completely damaged by ESD, ESD interference is very common. ESD interference may cause device lockup, reset, data loss or reduced reliability, and may even cause data bit ghosting, product damage, and even damage to electronic equipment. "Hard fault" or component failure. The result may be: in the cold and dry winter, electronic equipment often fails, but it is normal when repaired, which will inevitably affect the confidence of users in electronic equipment and its manufacturers. It can be seen that it is very necessary to consider ESD protection during the design of electronic products, especially the design of its PCB board.

2. The mechanism of ESD generation

What is ESD? How does ESD enter electronic equipment? ESD has the potential to occur when a charged conductor is in close proximity to another conductor. First, a strong electric field will be established between the two conductors, resulting in field-induced breakdown. An arc occurs when the voltage between two conductors exceeds the breakdown voltage of the air and insulating medium between them. In the time from 0.7ns to 10ns, the arc current will reach dozens of amperes, and sometimes even exceed 100A. The arc will continue until the two conductors touch short or the current is too low to sustain the arc. The generation of ESD depends on the initial voltage, resistance, inductance and parasitic capacitance of the object, for example: the human body, charged devices and machines may generate arcs, hands or metal objects may generate spike arcs, furniture may generate the same polarity or polarity changes Multiple arcs. ESD can enter electronic equipment through the following five coupling paths:

(1) The initial electric field can capacitively couple to the network with a large surface area, and generate a high voltage of up to 4000V/m at a distance of 100mm from the ESD arc.

(2) The charge/current injected by the arc can cause the following damage and failure: ① Penetrate the thin insulating layer inside the component and damage the gate of MOSFET and CMOS components (common). ②Flip-flop lockup in CMOS devices (common). ③Short-circuit reverse-biased PN junction (common). ④ Short circuit forward biased PN junction (rare). ⑤ Melt the welding wire or aluminum wire inside the active device (rare).

(3) The current will cause voltage pulses (V=L×dI/dt) to be generated on the conductors. These conductors may be power supply, ground or signal lines. These voltage pulses will enter every component connected to these networks (common).

(4) The arc will generate a strong magnetic field with a frequency range of 1 MHz to 500 MHz, and inductively couple to each adjacent wiring loop, generating a current up to 1 5A/m at a distance of 1 00 mm from the ESD arc.

(5) The electromagnetic field radiated by the arc will be coupled to long signal lines, which act as receiving antennas (rare). It can be seen that the ESD frequency range is wide, and it is possible to find the weak point of the device through various coupling paths.

In order to prevent ESD interference and damage, the anti-ESD ability of the equipment should be comprehensively considered from the following three aspects:

Selection of components: such as considering the ESD capacity of the chip, using a transient voltage suppressor (TVS) diode array, etc.; PCB layout design: such as increasing the grounding area as much as possible, shortening the PCB trace, etc.;

Mechanical design: For example, shielding measures such as plastic chassis and air space are used to effectively solve ESD problems.

Among them, PCB layout design is one of the most critical elements to optimize ESD protection. Reasonable PCB design can reduce unnecessary costs caused by fault inspection and rework.

3. Anti-ESD design method of PCB board

By analyzing the mechanism of ESD and its hazards, designers can consider optimizing the PCB design scheme for ESD protection from the following aspects:

3.1 Reduce circuit loop area

Current is induced into closed circuit loops that also have varying magnetic flux. The area of the loop is proportional to the magnitude of the current. The larger the area of the loop, the greater the magnetic flux contained, and thus the greater the current induced in the circuit. Therefore, it is necessary to reduce the loop area as much as possible during design.

Figure 1 shows one of the most common circuit loops, formed by power and ground. Where possible, a multilayer PCB design with power and ground planes can be used. The multi-layer circuit board not only minimizes the loop area between the power supply and the ground, but also the ground plane and the power plane, as well as the closely arranged signal line-ground spacing can reduce the common impedance (common impedance) and inductive coupling, and also reduce the The high-frequency EM I electromagnetic field generated by the ESD pulse is reduced.

If the use of multi-layer circuit boards is limited by conditions, then the grid structure shown in Figure 2 must be used for power lines and ground lines. The grid size of this grid structure is less than or equal to 60mm, and if possible, the grid size is preferably less than 1 3 mm (0. 5in.). Between vertical and horizontal lines or filled areas, connect as many as possible. Also, keeping the power and ground traces as close as possible can also reduce the loop area.

Another way to reduce loop area and induced current is to reduce parallel paths between interconnecting devices.

3.2 Shorten the length of the circuit connection

A long signal line can be used as an antenna for receiving ESD pulse energy. In the design, try to use a signal line less than 30cm to reduce the efficiency of the signal line as an antenna for receiving ESD electromagnetic fields. And try to put the interconnected devices in adjacent positions, so that the length of the interconnected printed lines is as short as possible.

When it is necessary to use a signal connection line longer than 30cm, a protection line can be used, as shown in Figure 5. The ground layer should be placed near the signal line, and the distance between the signal line and the ground line layer (or protection line) should be less than 1 3 mm (0. 5in.).

Another way is to cross the signal line or power line longer than 30cm and its grounding line. The crossed lines must be arranged at regular intervals from top to bottom or from left to right.

3.3 Protect all external connections with TVS diodes

Adding a TVS device on the power line can help solve the problem of ESD from the power port connected to the power supply. TVS connected to Vcc and ground can prevent ESD interference from the power supply, but the parasitic inductance in the protection circuit should be considered.

During an ESD event, the parasitic inductance in the TVS diode path can generate severe voltage overshoot. Although a TVS diode is used, the total voltage that the protection circuit can withstand is the sum of the clamp voltage of the TVS diode and the voltage generated by the parasitic inductance: V T=V C+VL, due to the induced voltage VL=L×dI/dt at both ends of the inductive load , the excessively high overshoot voltage may still exceed the damage voltage threshold of the protected IC. An ESD transient induced current can reach its peak value in less than 1 ns (according to the IEC 61 000-4-2 standard), for example: the lead inductance is 20nH per inch, and the line length is a quarter of an inch. The impulse voltage will be a pulse of 50V/1 0A. Therefore, the shunt path should be designed as short as possible in order to reduce the effect of parasitic inductance. Ground loops must be considered when designing all inductive paths, namely: the path between the TVS and the signal line to be protected, and the path from the connector to the TVS device. In order to reduce the parasitic inductance of the ground plane, the distance between the ground of the TVS diode and the ground point of the protected circuit should be as short as possible.

3.4 Reduce ground charge injection

Sensitive circuits may be damaged during direct discharge of ESD to the ground plane. Therefore, one or more high-frequency bypass capacitors must be used along with the TVS diodes to protect the power supply from ESD disturbances, as shown in Figure 7. These capacitors are connected between power and ground for vulnerable components. The bypass capacitor can reduce the injection of ground charge, so that the voltage difference between the power supply and the ground port is clamped. The TVS shunts the sense current and maintains the potential difference of the TVS clamping voltage. In addition, TVS and capacitors should be placed as close as possible to the protected IC. In order to reduce the effect of parasitic inductance, ensure that the path from TVS to ground and the length of capacitor pins are the shortest. The connector must be mounted to the copper-platinum plane on the PCB. Ideally, the copper-platinum layer must be isolated from the ground plane of the PCB and connected to the pad by a short wire.