Synchronous Switching Noise Analysis

Analysis of Synchronous Switching Noise Problems in PCB Design

As a large number of highly integrated high-speed digital chips are used on communication equipment circuit boards, the problem of simultaneous switching noise (Simultaneous Switching Noise, SSN) has become a bottleneck restricting high-speed PCB design. SSN means that when multiple logic circuits or I/O pins on the device are in the switching state at the same time, an instantaneously changing current is generated, and when there is an inductance on the return path, an AC voltage drop is formed, thereby causing noise. If the fluctuation of the ground plane is caused, causing the chip ground and the system ground to be inconsistent, this phenomenon is called ground bounce. Similarly, if there is a difference between chip power and system power, it is called power bounce.

1. Causes and hazards of synchronous switching noise (SSN)

According to the theory of power integrity, one of the main causes of SSN is the impedance of the power distribution system. Specifically, there is a distance from the output end of the power supply to the input end of the chip, and there is impedance on this path. From the point of view of the centralized model, it is equivalent to connecting concentratedly distributed resistance and inductance elements in series. When a certain number of output drive circuits are turned on at the same time, a large current will instantly rush into these inductive elements. The current will generate an induced electromotive force on the inductive element, causing the net supply voltage at the input terminal of the chip power supply to be insufficient or too high. Similarly, according to the theory of signal integrity, another important cause of SSN is the mutual inductance coupling, especially the mutual inductance coupling generated around the edge of the chip package and PCB. The solder balls on the chip BGA package and the vias on the PCB belong to a tightly coupled multi-conductor structure, and each I/O solder ball and its corresponding PCB via are formed by the nearest ground solder ball and ground via. A closed loop, when the state of multiple I/O ports changes at the same time, there will be transient I/O current flowing through these signal loops, and this transient I/O current will generate a changing magnetic field, thus Invasion of adjacent signal loops causes induced voltage noise.

The hazard of SSN is very great, it will increase power supply noise, affect signal quality and timing, and lead to missampling of digital circuits. In addition, the problems caused by SSN are generally hidden and only occur when multiple logic units of the device are switched on and off at the same time. It is difficult to find out with normal business testing methods and is easy to miss, which brings huge risks to the reliable operation of the equipment.

Based on the mechanism of synchronous switching noise, this paper designs a reliability test method that exposes the SSN problem, and uses this method to find a specific Serdes link abnormal problem. The defects in the PCB design were eliminated and modified. Finally, some methods for suppressing synchronous switching noise during output PCB design are summarized.

2. Simultaneous Switching Noise (SSN) Reliability Test Method

Reliability testing is to expose equipment to various possible extreme working conditions for verification, and to find system design defects. For synchronous switching noise, we can design test cases from the mechanism and common hazards. For example, when a large number of buses switch at the same time, crosstalk noise will be introduced on adjacent pins. In this case, it is necessary to impose a special service load on the device under test during test design, so that the bus is exposed to as much as possible Under the condition of large crosstalk, use an oscilloscope to observe whether the bus signal quality and timing are acceptable. Taking the 16-bit parallel bus as an example, in order to maximize this effect, when designing the test message, 15 of the 16 signals have the same transition direction, that is, all 15 signal lines transition from 0 to 1 at the same time. At the same time, let another interfered signal line jump from 1 to 0. A loop program can be designed to allow 16 lines to traverse this test scenario in turn.

In addition, synchronous switching noise may also affect sensitive signals on the return path. This is a very bad working state of the parallel bus. In order to verify whether the product works reliably under this working condition, it is necessary to add a special SSN test packets for verification. If the bus under test is 16 bits wide, to make all 16 signal lines flip synchronously, the message content should be: FFFF 0000; if the bus under test is 32 bits wide, to make all 32 signal lines flip synchronously, the test message The content should be: FFFF FFFF 0000 0000.

Of course, the working environment of the device may also be high or low temperature, and the impact of temperature on the circuit is very significant. For example, the capacitance of the capacitor will change at low temperature and high temperature, and the internal timing parameters of the device will drift at low temperature. At high temperature, the impedance of PCB traces becomes larger, etc. Therefore, when performing the above SSN reliability test, it is necessary to increase the temperature stress to verify the reliability of the system.

3. Synchronous switching noise suppression method

Through the analysis of the abnormal problem of Serdes link, it can be seen that the impact of synchronous switching noise on circuit reliability is increasing. With the continuous improvement of device speed, this impact will become more obvious. Then, how to avoid the harm caused by SSN problem as much as possible What? Generally, when designing a single-board PCB, we can refer to the following rules for design.

(1) For DDR storage devices, it is best not to run the data bus on the same layer to reduce the impact on the reference plane noise in the case of SSN; it can be considered to be placed on the same layer as the address bus, and the data bus is preferentially referred to its I/O power supply.

(2) Sensitive signals such as Serdes try to avoid walking on the edge of the reference plane.

(3) Sensitive signals such as Serdes and RAM data bus should be separated as far as possible on the PCB, and placed on different wiring layers to avoid referring to the same power plane.

(4) In the case of satisfying the flow, the power plane should not be too large. When there are high-speed I/O signals or Serdes sensitive signals refer to this plane, do ground laying where the power supply is not used.

(5) The power plane cannot have a large area without high-frequency decoupling capacitors. It is recommended to add decoupling capacitors especially where there are high-speed signal cross-segmentation on the edge of the plane. The decoupling capacitors can use discrete capacitors or embedded capacitors.

(6) Carry out simulation analysis and evaluation of power plane resonance, and try to avoid resonance with the operating frequency of storage devices.

(7) Add enough decoupling capacitors to the power input end close to the chip to stabilize the voltage, and it is best to use L-type or π-type LC filter circuits.

(8) The wiring layer of the I/O is preferably close to the TOP surface to reduce the loop inductance caused by the signal layer change.

(9) When the pins of the logic chip are arranged, the synchronous I/Os that are stacked together are spread out to reduce the loop inductance caused by space coupling, and the unused pins are grounded or power processed to increase the return path.

(10) Add a bypass capacitor in the chip or select a chip packaged with low impedance characteristics.

(11) For the suppression of synchronous switching noise at very high frequencies, high-impedance electromagnetic surface structure (EB G) can be considered. When using EB G structure as the PCB substrate, it can be integrated in the microstrip circuit substrate with a wide resistance When combined with other circuit components organically, it can save circuit space.

Summarize

In general, according to the bus structure of the logic unit or I/O interface on the board mentioned in the article, the test method of constructing a special message during the test phase and making these interfaces flip synchronously can quickly find design defects and expose the circuit board. The potential problem of synchronous switching noise is eliminated, and the reliability of the board is improved. At the same time, the method of suppressing synchronous switching noise summarized according to specific problems is not only the principle to be followed in the early design stage, but also the solution to the problem in the later stage. In the future, we can also use the equivalent model method to simulate and analyze the possible risk of synchronous switching noise on the board in the early stage to avoid problems in advance. It is also possible to design a programmable SSN test program, so that chip manufacturers can embed it in the controller, which can be directly invoked and verified during the reliability test stage to enhance the testability of the single board.

The above is the analysis of synchronous switching noise problems in PCB design introduced by Shenzhen Zuchuang Microelectronics Co., Ltd. for you. If you have software and hardware function development needs for smart electronic products, you can rest assured to entrust them to us. We have rich experience in customized development of electronic products, and can evaluate the development cycle and IC price as soon as possible, and can also calculate PCBA quotations. We are a number of chip agents at home and abroad: Songhan, Yingguang, Jieli, Ankai, Quanzhi, realtek, with MCU, voice IC, Bluetooth IC and module, wifi module. We have hardware design and software development capabilities. Covering circuit design, PCB design, single-chip microcomputer development, software custom development, APP custom development, WeChat official account development, voice recognition technology, Bluetooth wifi development, etc. It can also undertake the research and development of smart electronic products, the design of household appliances, the development of beauty equipment, the development of Internet of Things applications, the design of smart home solutions, the development of TWS earphones, the development of Bluetooth earphone speakers, the development of children's toys, and the research and development of electronic education products.